Research & Development Achievements and Plans

UMC has been actively engaging with new 65-nanometer customers and extending the product spectrum of manufactured products to range from low-power handheld applications in the GSM and CDMA wireless domain to high-performance networking, switching and computing graphic products. The UMC 55SP process (shrinking L65 feature sizes to 90% of its original size) has also successfully passed the qualification stage. This offering is expected to help customers migrate their 65-nanometer products for more density and performance while delivering more competitive cost incentives to further extend their product life. In addition to manufacturing success, UMC is constantly adding system-on-chip (SoC) variety into existing CMOS compatible processes. This includes adding a 65-nanometer RF CMOS solution, which features fundamental libraries, IP, and the foundry industry's first transformer library to help customers jump-start their design-in process. Full characterization reports, models with mismatch Monte Carlo simulation, advance HF noise model and foundry design kits (FDK) complement the 65-nanometer RF process, with RF SPICE models and ESD manuals and support ready. This offering is targeted for next generation wireless system-on-chip (SoC) applications including WiFi, WiMax, wireless USB, and cellular.

During 2007, UMC focused on improving transistor performance and defect density to meet 45-nanometer mass-production goals and preparing the technology for adoption by our foundry customers. UMC has successfully delivered functional samples with an SRAM bit cell size of less than 0.26um2 for customers' product validation. UMC is among the first companies in the world to produce working 45-nanometer silicon, with successful results realized for the initial 45-nanometer wafer lots. In addition, UMC is in the final process optimization stage of a shrink version of its 45-nanometer process technology, called the UMC 40SP process (shrinking L45 feature sizes to 90% of its original size). This offering is expected to help customers migrate their 45-nanometer products for more density and performance while delivering more competitive cost incentives to further extend their product life.

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SoC Enabling Technologies

SoC designers today require proven design support solutions to help them overcome the challenges encountered during the design cycle. UMC has successfully introduced a Reference Design Flow with silicon-proven design methodologies in 90-nanometer and 65-nanometer technologies. The UMC Reference Design Flows incorporate 3rd-party EDA vendors' baseline design flows to address issues such as timing closure, signal integrity, leakage power and Design For Manufacturability (DFM). The flow has been successfully validated utilizing the open-source LEON2 SPARC processor in 65-nanometer silicon. They cover schematic/RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. The availability of UMC's newest and most comprehensive reference flows help SoC designers find the easiest path to silicon success for advanced technologies. In order to address customer's SoC design needs of intellectual properties (IP), UMC operates an extensive coverage of 3rd-party IP partnerships with industry-leading vendors including ARM, Virage, Synopsys, Faraday, and Silicon Image, offering a range of services from physical libraries to analog mixed-signal IP that supports industry standards such as PCI-E, SATA, and HDMI. In addition, UMC successfully developed a series of reliable, high quality intellectual properties (IP). These include DFM-compliant, process-tuned 65-nanometer libraries, ultra high-speed PLL, and various state-of-the-art analog mixed-signal IPs that support industry standards for advanced audio/video applications, all of which will be utilized in customer SoC designs to help shorten their design cycle time.

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Fundamental Research

For exploratory technologies, the true limits of immersion lithography are being constantly challenged, while further Resolution Enhancement Techniques (RETs) are being explored actively for 32-nanometer and below technology. The mini-pilot line for high-k dielectric/metal gate development has narrowed down the number of material choices for dual work function metal gates and a possible integration scheme to enable such new materials. The search for new advanced CMOS device schemes leads to multi-gate field-effect transistors (MuGFETs), and various mobility enhancement structures. The new and innovative transistor scheme is being explored for 32 and beyond technology development.

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